verilog - Error: <signal> is not a constant -

module concat(     input [7:0] data_in,     input rst,     input clk,     output reg[127:0] data_out,     output reg valid_out     );      integer i;      reg[127:0] datatemp=0;  always@(data_in) begin     if(rst)     begin         data_out<=0;         datatemp<=0;     end     else     begin     for(i=0;i<=127;i=i+8)     begin         datatemp[i:i+7]<=data_in;     end         if(i==127)         begin             valid_out<=1;             data_out<=datatemp;         end     end end   endmodule 

this code showing following error:

line 44: not constant

please tell me how remove it. i'd grateful.

it looks ended loop soon. checking value of being equal 127 after loop done. think code compile want this:

for(i=0;i<=127;i=i+8) begin     datatemp[i:i+7]<=data_in;     if(i==127)     begin         valid_out<=1;         data_out<=datatemp;     end end 

but sure want do? understand in verilog for-loops unrolled? different how behave in c or java or software language. i'm not sure why ever need check value of i, unless not understanding how for-loops work in synthesizable verilog.