Instantiation of multi architecture vhdl enity in verilog testbench -

i have develop verilog tb design in vhdl. design has multiple entities each entity has multiple architectures. want develop verilog wrapper around each entity , use wrapper communicate test bench. entity has different architecture different testcase, approach each testcase has compile separately. there better way of doing ?? suggestions uvm implementation ?

this simulator-specific. modelsim, example, verilog tb can instantiate entity, entity/architecture pair, or configuration (which want). i'd surprised if incisive can't - check manuals.