What is the minimum number of bits I need to express a n-bit, signed std_logic_vector in VHDL? -

i'm new vhdl , trying find way take n bit (stored generic) signed number , truncate form requires minimum number of bits.

for example, if have 5 8 bit signed number (stored in std_logic_vector of length 8) 00000101, i'd make function return 0101 std_logic_vector. ideas on how can accomplish this?

since have specified you're using signed value, may want use signed type (from numeric_std library) instead of more generic std_logic_vector.

if number compile time constant, can write function starting leftmost bit (in loop example) counts how many identical bits sees, returns signed_input(8-result downto 0). issue compile time constant, there isn't advantage in removing redundant bits. whole vector optimized away in synthesis.

you might want include special cases make result @ least 1 bit (0 technically doesn't need bits represest) or 2 bits (-1 needs sign bit distinguish 0) depending on how want use signed type value.

if number real signal (the value changes during operation), can still count number of identical bits left, variable location slicing of vector iffy. trying pack of several numbers fixed bit width? doing synthesize multiplexers each bit luts used calculating number of redundant bits each of numbers.